C161 Datasheet, PDF (86/400 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

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The table below lists the vector locations for hardware traps and the corresponding
status flags in register TFR. It also lists the priorities of trap service for cases, where
more than one trap condition might be detected within the same instruction. After any
reset (hardware reset, software reset instruction SRST, or reset by watchdog timer
overflow) program execution starts at the reset vector at location 00’0000_H. Reset
conditions have priority over every other system activity and therefore have the highest
priority (trap priority III).
Software traps may be initiated to any vector location between 00’0000_H and 00’01FC_H.
A service routine entered via a software TRAP instruction is always executed on the
current CPU priority level which is indicated in bit field ILVL in register PSW. This means
that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.
Table 5-2 Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
Location Number Prio
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
Class B Hardware Traps:
Undefined Opcode
UNDOPC
Protected Instruction Fault PRTFLT
Illegal Word Operand Access ILLOPA
Illegal Instruction Access
ILLINA
Illegal External Bus Access ILLBUS
Reserved
Software Traps:
TRAP Instruction
RESET
RESET
RESET
00’0000_H 00_H
00’0000_H 00_H
00’0000_H 00_H
NMITRAP 00’0008_H 02_H
STOTRAP 00’0010_H 04_H
STUTRAP 00’0018_H 06_H
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028_H 0A_H
00’0028_H 0A_H
00’0028_H 0A_H
00’0028_H 0A_H
00’0028_H 0A_H
[2C_H – 3C_H] [0B_H –
0F_H]
Any
Any
[00’0000_H – [00_H –
00’01FC_H] 7F_H]
in steps
of 4_H
III
III
III
II
II
II
I
I
I
I
I
Current
CPU
Priority
User’s Manual
5-4
1999-08