C161 Datasheet, PDF (337/400 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

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19.3
Power Down Mode
The microcontroller can be switched to Power Down mode which reduces the power
consumption to a minimum. Clocking of all internal blocks is stopped (RTC and selected
oscillator optionally), the contents of the internal RAM, however, are preserved through
the voltage supplied via the V_DD pins. The watchdog timer is stopped in Power Down
mode. This mode can only be terminated by an external hardware reset, i.e. by asserting
a low level on the RSTIN pin. This reset will initialize all SFRs and ports to their default
state, but will not change the contents of the internal RAM.
There are two levels of protection against unintentionally entering Power Down mode.
First, the PWRDN (Power Down) instruction which is used to enter this mode has been
implemented as a protected 32-bit instruction. Second, this instruction is effective only
if the NMI (Non Maskable Interrupt) pin is externally pulled low while the PWRDN
instruction is executed. The microcontroller will enter Power Down mode after the
PWRDN instruction has completed.
This feature can be used in conjunction with an external power failure signal which pulls
the NMI pin low when a power failure is imminent. The microcontroller will enter the NMI
trap routine which can save the internal state into RAM. After the internal state has been
saved, the trap routine may then execute the PWRDN instruction. If the NMI pin is still
low at this time, Power Down mode will be entered, otherwise program execution
continues.
The initialization routine (executed upon reset) can check the reset identification flags in
register WDTCON to determine whether the controller was initially switched on, or
whether it was properly restarted from Power Down mode.
The realtime clock (RTC) can be kept running in Power Down mode in order to maintain
a valid system time as long as the supply voltage is applied. This enables a system to
determine the current time and the duration of the period while it was down (by
comparing the current time with a timestamp stored when Power Down mode was
entered). The supply current in this case remains well below 1 mA.
During power down the voltage at the V_DD pins can be lowered to 2.7 V while the RTC
and its selected oscillator will still keep on running and the contents of the internal RAM
will still be preserved.
When the RTC (and oscillator) is disabled the internal RAM is preserved down to a
voltage of 2.5 V.
Note: When the RTC remains active in Power Down mode also the oscillator which
generates the RTC clock signal will keep on running, of course.
If the supply voltage is reduced the specified maximum CPU clock frequency for
this case must be respected.
User’s Manual
19-7
1999-08