C161 Datasheet, PDF (340/400 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

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19.4
Slow Down Operation
A separate clock path can be selected for Slow Down operation bypassing the basic
clock path used for standard operation. The programmable Slow Down Divider (SDD)
divides the oscillator frequency by a factor of 1...32 which is specified via bitfield
CLKREL in register SYSCON2 (factor = <CLKREL>+1). When bitfield CLKREL is written
during SDD operation the reload counter will output one more clock pulse with the „old“
frequency in order to resynchronize internally before generating the „new“ frequency.
If direct drive mode is configured clock signal f_DD is directly fed to f_CPU, if prescaler mode
is configured clock signal f_DD is additionally divided by 2:1 to generate f_CPU (see
examples below).
CLKREL
f_OSC
f_SDD
Reload Counter
f_OSC
factor=3, direct drive
f_SDD
factor=5, direct drive
factor=3, prescaler
Figure 19-3 Slow Down Divider Operation
Using e.g. a 5 MHz input clock the on-chip logic may be run at a frequency down to
156.25 KHz (or 78 KHz) without an external hardware change. An implemented PLL
may be switched off in this case or kept running, depending on the requirements of the
application (see table below).
Note: During Slow Down operation the whole device (including bus interface and
generation of signals CLKOUT or FOUT) is clocked with the SDD clock (see figure
above).
User’s Manual
19-10
1999-08