C161 Datasheet, PDF (200/400 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

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Timer 3 in Counter Mode
Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘001_B’. In counter mode timer T3 is clocked by a transition at the external input pin
T3IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this pin. Bit field T3I in control
register T3CON selects the triggering transition (see table below).
Edge
Select
TxIN
Txl
TxUD
TxEUD
T3IN = P3.6
T3EUD = P3.4
T3OUT = P3.3
XOR
TxR
0
MUX
1
TxUDE
Core Timer Tx
Up/
Down
TxOTL
TxOE
TxOUT
Interrupt
Request
x=3
MCB02030
Figure 10-5 Block Diagram of Core Timer T3 in Counter Mode
Table 10-3
T3I
000
001
010
011
1XX
GPT1 Core Timer T3 (Counter Mode) Input Edge Selection
Triggering Edge for Counter Increment / Decrement
None. Counter T3 is disabled
Positive transition (rising edge) on T3IN
Negative transition (falling edge) on T3IN
Any transition (rising or falling edge) on T3IN
Reserved. Do not use this combination
User’s Manual
10-8
1999-08