C161 Datasheet, PDF (364/400 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

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20.4
Table Searching
A number of features have been included to decrease the execution time required to
search tables. First, branch delays are eliminated by the branch target cache after the
first iteration of the loop. Second, in non-sequentially searched tables, the enhanced
performance of the ALU allows more complicated hash algorithms to be processed to
obtain better table distribution. For sequentially searched tables, the auto-increment
indirect addressing mode and the E (end of table) flag stored in the PSW decrease the
number of overhead instructions executed in the loop.
The two examples below illustrate searching ordered tables and non-ordered tables,
respectively:
MOV
LOOP:
CMP
JMPR
R0, #BASE
R1, [R0+]
cc_SGT, LOOP
;Move table base into R0
;Compare target to table entry
;Test whether target has not been found
Note: The last entry in the table must be greater than the largest possible target.
MOV
LOOP:
CMP
JMPR
R0, #BASE
R1, [R0+]
cc_NET, LOOP
;Move table base into R0
;Compare target to table entry
;Test whether target is not found AND..
;..the end of table has not been reached.
Note: The last entry in the table must be equal to the lowest signed integer (8000_H).
20.5
Floating Point Support
All floating point operations are performed using software. Standard multiple precision
instructions are used to perform calculations on data types that exceed the size of the
ALU. Multiple bit rotate and logic instructions allow easy masking and extracting of
portions of floating point numbers.
To decrease the time required to perform floating point operations, two hardware
features have been implemented in the CPU core. First, the PRIOR instruction aids in
normalizing floating point numbers by indicating the position of the first set bit in a GPR.
This result can the be used to rotate the floating point result accordingly. The second
feature aids in properly rounding the result of normalized floating point numbers through
the overflow (V) flag in the PSW. This flag is set when a one is shifted out of the carry bit
during shift right operations. The overflow flag and the carry flag are then used to round
the floating point result based on the desired rounding algorithm.
User’s Manual
20-12
1999-08