TLE8263-2E Datasheet, PDF (84/94 Pages) Infineon Technologies AG – Universal System Basis Chip

TLE8263-2E
Confidential
Serial Peripheral Interface
15.7
Electrical Characteristics
V_S = 5.5 V to 28 V; T_j = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Pos. Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
SPI Interface; Logic Inputs SDI, CLK and CSN
15.7.1 H-input Voltage Threshold V_IH
15.7.2 L-input Voltage Threshold V_IL
15.7.3
15.7.4
Hysteresis of input
Voltage
Pull-up Resistance at pin
CSN
V_IHY
R_ICSN
–
–
0.3 x
V_CC1µC
20
–
0.12 x
V_CC1µC
40
0.7 x V
V_CC1µC
–
V
V
80
kΩ
–
–
–¹⁾
V_CSN = 0.7 × V_CC1µC
15.7.5 Pull-down Resistance at R_ICLK/SDI 20
40
pin SDI and CLK
80
kΩ
V_SDI/CLK = 0.2 × V_CC1µC
15.7.6 Input Capacitance
C_I
–
10
-
at pin CSN, SDI or CLK
pF -1)
Logic Output SDO
15.7.7 H-output Voltage Level
V_SDOH
V_CC1µC - V_CC1µC - –
0.4
0.2
V
I_DOH = -1.6 mA
15.7.8 L-output Voltage Level
V_SDOL
–
0.2
0.4
V
I_DOL = 1.6 mA
15.7.9 Tri-state Leakage Current I_SDOLK -10
–
15.7.10 Tri-state Input
Capacitance
Data Input Timing¹⁾
15.7.11 Clock Period
C_SDO
–
10
t_pCLK
250
–
10
µA
V_CSN = V_CC1µC;
0 V < V_DO < V_CC1
15
pF 1)
–
ns –
15.7.12 Clock High Time
t_CLKH
125
–
–
ns –
15.7.13 Clock Low Time
t_CLKL
125
–
–
ns –
15.7.14 Clock Low before CSN t_bef
Low
15.7.15 CSN Setup Time
t_lead
125 –
250 –
–
ns –
–
ns –
15.7.16 CLK Setup Time
t_lag
250 –
–
ns –
15.7.17 Clock Low after CSN High t_beh
125 –
–
ns –
15.7.18 SDI Set-up Time
t_DISU
100
–
–
ns –
15.7.19 SDI Hold Time
t_DIHO
50
–
–
ns –
Data Sheet
84
Rev. 1.0, 2009-03-31