TLE8263-2E Datasheet, PDF (74/94 Pages) Infineon Technologies AG – Universal System Basis Chip

Confidential
15.4
SPI Output Data
TLE8263-2E
Serial Peripheral Interface
MSB
LSB
Output _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
Data
CS2 CS1 CS0 MS2 MS1 MS0
WK
state
Configuration Registers
Configuration Select ^{Mode Selection}
Bits
INT
Res.
Cyclic WK 1 WK 0
WK WK pin WK pin
Res.
WK
LIN2
WK WK
LIN1 CAN
000
Init
000
Status or
INTERRUPT
event
Wrong
WD set
Reset
Fail
SPI
I_CC3 >
ICC3max
UV
Vcc3
UV
VCC2
OT OT OTP
VCC2 HS CAN Vcc1µC
Res.
Res.
LIN 2 LIN2 LIN1 LIN1
failure failure failure failure
1
0
1
0
CAN
Bus
CAN CAN
failure failure
1
0
Reserved
001
010
011
Restart
001
SW Flash ⁰¹⁰
Normal
011
Cyclic
WD to
LH
WK
L.H. VCC2 WK PIN VCC3 Reset
On/off On/Off On /off On/off Delay
RT1
On /off
RT0
100
REGISTER
LIN CAN CAN
10.4k 1
0
Res.
Res.
LIN2 LIN 2 LIN1 LIN 1
1
0
1
0
101
CHK WD
SUM On/Off
Ti.
Out /
Win.
Set to
1
Window /Time out Watchdog
Timing Bit Position: 10 .. 6
110
111
Res. RM1 RM0 LH 2 LH 1 LH 0 Test 2 Test 1 Test 0
Sleep
100
101
Stop
110
Fail Safe
Reserved
111
SPI_Settings_out_TLE8263.vsd
Figure 38 16-bit SPI Output Data / Control Word
15.5
SPI Data Encoding
15.5.1 WD Refresh bit / WK state
The WD Refresh bit is used to trigger the Watchdog. The first trigger should be a 1, and then a 0. For more details,
please refer to Chapter 11.2.
The WK state bit gives the voltage level at the WK pin. A 1 indicates a high level, a 0 a low level.
Data Sheet
74
Rev. 1.0, 2009-03-31