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TLE8263-2E Datasheet, PDF (83/94 Pages) Infineon Technologies AG – Universal System Basis Chip
TLE8263-2E
Confidential
Serial Peripheral Interface
15.6.2 Read Only command
In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are
selected in the Configuration Select (some interrupt bits show a state, and can not be cleared with a SPI read).
With this SPI command no write access is done to the SBC, and the mode of the SBC is not changed. The
watchdog can also be triggered with a Read Only command.
The Read Only command delivers the information requested with the Configuration Select in the same SPI
command on the SDO pin. As all other SPI commands deliver the requested information with the next SPI
command.
Figure 39 shows an example of a Read Only access. The bits are shown with LSB first, on the left side in
difference to the register description.
DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection Configuration Select
Bits
111000x
Configuration Registers
xxxxxxx
WD
refresh
xx
DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection Configuration Select
Bits
110111x
Configuration Registers
xxxxxxx
WD
refresh
xx
DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection
Configuration Select
Bits
110000x
Configuration Registers
xxxxxxx
WK
state
xx
DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection
Configuration Select
Bits
110100x
Configuration Registers
xxxxxxx
WK
state
xx
TIME
Figure 39 Read Only Command
Figure 40 shows an example of an SPI write access in normal mode for comparison. The requested information
is sent out with the next SPI command.
DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection Configuration Select
Bits
110000x
Configuration Registers
xxxxxxx
WD
refresh
xx
DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection Configuration Select
Bits
110111x
Configuration Registers
xxxxxxx
WD
refresh
xx
DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection
Configuration Select
Bits
110100x
Configuration Registers
xxxxxxx
WK
state
xx
Figure 40 Write Command
DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS0 MS1 MS2 CS0 CS1 CS2
Mode Selection
Configuration Select
Bits
110000x
Configuration Registers
xxxxxxx
WK
state
xx
TIME
Data Sheet
83
Rev. 1.0, 2009-03-31