TLE8263-2E Datasheet, PDF (40/94 Pages) Infineon Technologies AG – Universal System Basis Chip

Confidential
9
WK Pin
9.1
Block Description
Internal supply
I_{PU_MON}
TLE8263-2E
WK Pin
IWK
State
machine
I_{PD_MON}
W ake.vsd
Figure 16 Functional Block Diagram
The internal voltage regulator (V_cc1µC) and the entire SBC can wake up by changing the wake input voltage. The
WK input pin is a bi-level sensitive input. This means that both transitions, HIGH to LOW and LOW to HIGH, result
in a wake-up. The filtering time is t_{WK, f.}The wake-up capability can be enabled or disabled via SPI command. In
case of reverse polarity, no special protection must be set if the absolute maximum rating is respected. When the
SBC is below the minimum V_UVOFF, (SBC OFF Mode) the pin WK is at high impedance; a wake event will be
ignored.
The state of the WK pin (low or high) can always be read in Normal Mode, Stop Mode and SW Flash Mode at the
bit WK State. When setting the bit “WK PIN on/off” to 1, the device wakes up from Sleep Mode with a high to low
or low to high transition. From Fail-Safe Mode the device will always go to Restart Mode with a high to low or low
to high transition. If the bit “WK PIN on/off” is set to 1 in Normal, Stop or SBC SW Flash Mode the interrupt bits
“WK 0 WK pin” and/or “WK 1 WK pin” are set in case of a change on the WK pin and an interrupt is generated if
not masked. With the bits “WK 0 WK pin” and “WK 1 WK pin” the interrupt for low to high transition and high to low
transition can be masked separately.
9.2
Wake-Up Timing
Figure 17 shows typical wake-up timing and parasitic filtering. The filtering time is t_{WK, f.}. This is used to avoid a
parasitic wake-up due to EMC disturbances. Specifically, the voltage transition on pin WK must be higher than the
V_WK,TH and longer than t_WK,f to be understood as a wake-up signal.
Data Sheet
40
Rev. 1.0, 2009-03-31