TLE8263-2E Datasheet, PDF (64/94 Pages) Infineon Technologies AG – Universal System Basis Chip

TLE8263-2E
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Interrupt Function
12.2
Interrupt Timing
Figure 30 illustrates the interrupt timing. The INT output is set LOW as soon as an interrupt condition occurs. The
INT pin is released after a SPI interrupt buffer read out command, that is performed with a Read Only command
(111) to register (000). In case consecutive interrupt sources are indicated before the SPI read out, only one INT
LOW will be raised but the SPI read out will indicate the interrupt sources. A time-out feature is implemented. The
INT pin can be active LOW only for the time t_INTTO. Afterwards, the INT pin is released but the INT source is still
valid or present in the SPI register. Between two activations of the INT, there is at least a delay of t_INTTO. If an
interrupt occurs in the meantime, the information is stored and the INT will go LOW after t_INTO. The INT pulse width
is at minimum t_INT.
interrupt source 1
active
inactive
interrupt source 2
active
inactive
INT output
t_INT
t_{INT TO}
SPI read out
SPI read out
Figure 30 Interrupt Timing
t_INTTO
SPI read out
t_INTTO
t
t
t_INTTO
SPI read out
t
interupt timing.vsd
12.3
Interrupt Modes with SBC Modes
The interrupt function is possible only in SBC Normal and Stop Mode.
After an SBC Restart Mode, all interrupt sources are enabled.
12.4
Interrupt Application Information
By default, all interrupt sources are activated. Please refer to the dedicated chapter for the definition of the
interrupt.
The INT output is active for at least t_INT, even if the corresponding interrupt register is read out immediately after
the interrupt event occurs.
If no SPI read is done after the interrupt is generated (INT pin low) the INT output becomes active (INT pin high)
again after t_INTTO.
If two interrupt cases occur after each other and the SPI read (with read-only) is done after the second interrupt
case, both interrupt bits are cleared. Although the interrupt bits for both interrupt cases are cleared the second
interrupt will be issued by INT pin Low. This can lead to an interrupt where all interrupt bits are read as “0”.
Data Sheet
64
Rev. 1.0, 2009-03-31