HYS72D128300GBR Datasheet, PDF (8/45 Pages) Infineon Technologies AG – 184-Pin Registered Double Data Rate SDRAM Module

HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
2
Pin Configuration
Table 3 Pin Definitions and Functions
Symbol
Type
A0 - A11,A12
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS,CAS,WE
CKE0, CKE1
DQS0 - DQS8
CK0, CK0
DM0 - DM8
DQS9 - DQS17
S0 - S1
V_DD
V_SS
V_DDQ
V_DDID
V_DDSPD
V_REF
SCL
SDA
SA0 - SA2
NC
DU
RESET
Function
Address Inputs
Bank Selects
Data Input/Output
Check Bits (×72 organization only)
Command Inputs
Clock Enable
SDRAM low data strobes
Differential Clock Input
SDRAM low data mask/
high data strobes
Chip Selects
Power (+2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Serial bus data line
slave address select
no connect
don’t use
Reset pin (forces register inputs low)¹⁾
1) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at
the end of this datasheet
Data Sheet
8
Rev. 0.5, 2003-12