HYS72D128300GBR Datasheet, PDF (23/45 Pages) Infineon Technologies AG – 184-Pin Registered Double Data Rate SDRAM Module

HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 13 AC Timing - Absolute Specifications –7/–7F
Parameter
Symbol
–7F
DDR266
Min. Max.
Address and control input hold time
t_IH
0.9 —
–7
DDR266A
Min. Max.
0.9 —
Unit Note/ Test
Condition
1)1)
ns fast slew
rate
3)4)5)6)10)
1.0 —
1.0 —
ns slow slew
rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command
period
t_RPRE
t_RPST
t_RAS
t_RC
t_RFC
0.9
0.40
45
65
75
1.1
0.9
0.60 0.40
120E+3 45
—
65
—
75
1.1
t_CK
0.60
t_CK
120E+3 ns
—
ns
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Read or Write delay
t_RCD
Precharge command period
t_RP
Active to Autoprecharge delay
t_RAP
Active bank A to Active bank B command
t_RRD
Write recovery time
t_WR
Auto precharge write recovery + precharge time t_DAL
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t_WTR
t_XSNR
t_XSRD
t_REFI
20 —
20 —
20 —
15 —
15 —
(t_WR/t_CK) +
(t_RP/t_CK)
1
—
75 —
200 —
— 7.8
20 —
20 —
20 —
15 —
15 —
(t_WR/t_CK) +
(t_RP/t_CK)
1
—
75 —
200 —
— 7.8
ns
2)3)4)5)
ns
2)3)4)5)
ns
2)3)4)5)
ns
2)3)4)5)
ns
2)3)4)5)
t_CK
2)3)4)5)11)
t_CK
2)3)4)5)
ns
2)3)4)5)
t_CK
2)3)4)5)
µs
2)3)4)5)12)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between V_OH(ac) and V_OL(ac).
Data Sheet
23
Rev. 0.5, 2003-12