HYS72D128300GBR Datasheet, PDF (31/45 Pages) Infineon Technologies AG – 184-Pin Registered Double Data Rate SDRAM Module

HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Table 16 SPD Codes for HYS72D[128/256][300/321/320]GBR–7–B
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Label Code
Jedec SPD Revision
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
Data Width (MSB)
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non- / ECC)
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
1 GB
×72
1 Rank
reg
PC2100R–20330
Rev. 0.0
HEX
80
08
07
0D
0C
01
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C1
75
75
00
1 GB
×72
2 Ranks
reg
PC2100R–20330
Rev. 0.0
HEX
80
08
07
0D
0B
02
48
00
04
70
75
02
82
08
08
01
0E
04
0C
01
02
26
C1
75
75
00
2 GB
×72
2 Ranks
reg
PC2100R–20330
Rev. 0.0
HEX
80
08
07
0D
0C
02
48
00
04
70
75
02
82
04
04
01
0E
04
0C
01
02
26
C1
75
75
00
Data Sheet
31
Rev. 0.5, 2003-12