XC164CS Datasheet, PDF (67/71 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

XC164
Derivatives
Timing Parameters
Table 19 External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
min. max.
Output valid delay for:
RD, WR(L/H)
tc₁₀ CC 1
13 ns
Output valid delay for:
A23…A16, BHE, ALE
tc₁₁ CC -1
7
ns
Output valid delay for:
A15…A0 (on PORT1)
tc₁₂ CC 1
16 ns
Output valid delay for:
A15…A0 (on PORT0)
tc₁₃ CC 3
16 ns
Output valid delay for:
CS
tc₁₄ CC 1
14 ns
Output valid delay for:
D15…D0 (write data, mux-mode)
tc₁₅ CC 3
17 ns
Output valid delay for:
D15…D0 (write data, demux-mode)
tc₁₆ CC 3
17 ns
Output hold time for:
RD, WR(L/H)
tc₂₀ CC -3
3
ns
Output hold time for:
A23…A16, BHE, ALE
tc₂₁ CC 0
8
ns
Output hold time for:
A15…A0 (on PORT0)
tc₂₃ CC 1
13 ns
Output hold time for:
CS
tc₂₄ CC -3
3
ns
Output hold time for:
D15…D0 (write data)
tc₂₅ CC 1
13 ns
Input setup time for:
READY, D15…D0 (read data)
tc₃₀ SR 24
–
ns
Input hold time
READY, D15…D0 (read data)¹⁾
tc₃₁ SR -5
–
ns
1) _{Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge}
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Note: The shaded parameters have been verified by characterization.
They are not 100% tested.
Data Sheet
63
V2.1, 2003-06