XC164CS Datasheet, PDF (18/71 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

XC164
Derivatives
Functional Description
3
Functional Description
The architecture of the XC164 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resoures as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164.
PSRAM
ProgMem
Flash / RO M
128 KBytes
OCDS
Debug Support
Osc / PLL RTC WDT
XTAL _{Clock G eneration}
DPRAM
CPU
C166SV2-Core
DSRAM
EBC
XBUS Control
External Bus
C on trol
Interrupt & PEC
Interrupt Bus
Peripheral D ata Bus
ADC
8/ 1 0 -B it
12/16
C h a nn e ls
GPT
T2
T3
T4
T5
T6
ASC0 ASC1 SSC0 SSC1
(USART) (USART) (S PI) (SPI)
BRGen BRGen BRGen BRGen
CC1
T0
T1
CC2
T7
T8
P 20 Port 9
Port 5
Port 4
Port 3
56
14
8
14
Figure 3 Block Diagram
CC6
T12
T13
Twin
CAN
AB
PORT1
16
PORT0
16
M C B04323_x4.vsd
Data Sheet
14
V2.1, 2003-06