XC164CS Datasheet, PDF (20/71 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

XC164
Derivatives
Functional Description
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC164 Memory Map¹⁾
Address Area
Start Loc. End Loc. Area Size²⁾ Notes
Flash register space FF’F000_H FF’FFFF_H
4 Kbytes Flash only³⁾
Reserved (Acc. trap) F8’0000_H FF’EFFF_H <0.5 Mbytes Minus Flash regs
Reserved for PSRAM E0’0800_H F7’FFFF_H <1.5 Mbytes Minus PSRAM
Program SRAM
E0’0000_H E0’07FF_H
2 Kbytes Maximum
Reserved for pr. mem. C2’0000_H DF’FFFF_H < 2 Mbytes Minus Flash/ROM
Program Flash/ROM C0’0000_H C1’FFFF_H 128 Kbytes
Reserved
BF’0000_H BF’FFFF_H 64 Kbytes
External memory area 40’0000_H BE’FFFF_H < 8 Mbytes Minus res. seg.
External IO area⁴⁾
20’0800_H 3F’FFFF_H < 2 Mbytes Minus TwinCAN
TwinCAN registers
20’0000_H 20’07FF_H
2 Kbytes
External memory area 01’0000_H 1F’FFFF_H < 2 Mbytes Minus segment 0
Data RAMs and SFRs 00’8000_H 00’FFFF_H 32 Kbytes Partly used
External memory area 00’0000_H 00’7FFF_H 32 Kbytes
1) _{Accesses to the shaded areas generate external bus accesses.}
2) _{The areas marked with “<“ are slightly smaller than indicated, see column “Notes”.}
3) _{Not defined register locations return a trap code.}
4) _{Several pipeline optimizations are not active within the external IO area. This is necessary to control external}
peripherals properly.
Data Sheet
16
V2.1, 2003-06