C165H Datasheet, PDF (61/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165H
Central Processor Unit
I_n+1
: ....
I_n+2
: POP R0
; must not be an instruction popping operands
; from the system stack
; pop word value from new top of stack into R0
Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved
internally by the CPU logic.
• External Memory Access Sequences
The effect described here will only become noticeable, when watching the external
memory access sequences on the external bus (eg. by means of a Logic Analyzer).
Y ^{Different pipeline stages can simultaneously put a request on the External Bus Controller}
(EBC). The sequence of instructions processed by the CPU may diverge from the
sequence of the corresponding external memory accesses performed by the EBC, due
R to the predefined priority of external memory accesses:
1st Write Data
A ^{2nd Fetch Code}
3rd Read Data.
IN ^{- • Controlling Interrupts}
T ^{Software modifications (implicit or explicit) of the PSW are done in the execute phase of}
the respective instructions. In order to maintain fast interrupt responses, however, the
IM ^{P current interrupt prioritization round does not consider these changes, ie. an interrupt}
request may be acknowledged after the instruction that disables interrupts via IEN or
L ^{R ILVL or after the following instructions. Timecritical instruction sequences therefore}
should not begin directly after the instruction disabling interrupts, as shown in the
E ^{E following example:}
INT_OFF: BCLR IEN
R ^{C IN-1}
CRIT_1ST: I_N
X ^{. . .}
CRIT_LAST: I_N+x
P^{INT_ON: BSET IEN}
; globally disable interrupts
; non-critical instruction
; begin of uninterruptable critical sequence
; end of uninterruptable critical sequence
; globally re-enable interrupts
- ^{E Note: The described delay of 1 instruction also applies for enabling the interrupts system}
ie. no interrupt requests are acknowledged until the instruction following the
enabling instruction.
• Initialization of Port Pins
Modifications of the direction of port pins (input or output) become effective only after the
instruction following the modifying instruction. As bit instructions (BSET, BCLR) use
internal read-modify-write sequences accessing the whole port, instructions modifying
Data Sheet
61
2001-04-19