C165H Datasheet, PDF (273/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165H
Asynchronous/Synchr. Serial Interface
Table 56
Autobaud Detection using Standard Baudrates (f_DIV = 11.0592 MHz)
Baudrate
Numbering
Detectable Standard
Baudrate
Divide Factor d _f
BG is loaded after
detection with value
Br5
9600 Baud
1152
71
= 047_H
Br6
4800 Baud
2304
143 = 08F_H
Br7
2400 Baud
Br8
1200 Baud
4608
9216
287 = 11F_H
575 = 23F_H
According Table 56 a baudrate of 9600 Baud is achieved when register BG is loaded
with a value of 047_H, assuming that f_DIV has been set to 11.0592 MHz.
Y _{Table 56 also lists a divide factor d f which is defined with the following formula :}
R ^{Baudrate =}
f _DIV
d_f
This divide factor d_f defines a fixed relationship between the prescaler output frequency
A _{fDIV and the baudrate to be detected during the autobaud detection operation. This}
means, changing f_DIV results in a totally different baudrate table in means of baudrate
IN ^{- values. For the baudrates to be detected, the following relations are always valid :}
– Br0 = f_DIV / 48_D, Br1 = f_DIV / 96_D, ....... up to Br8 = f_DIV / 9216_D,
T A requirement for detecting standard baudrates up to 230.400 kBaud is the f_DIV minimum
value of 11.0592 MHz. With the value FD_VALUE in register FDV the fractional divider
IM ^{P fDIV is adapted to the module clock frequency fMOD. Table 57 defines the deviation of the}
standard baudrates when using autobaud detection depending on the module clock
L ^{R fMOD.}
Table 57 Standard Baudrates - Deviations and Errors for Autobaud Detection
E ^E _fMOD
R ^{C 10 MHz}
12 MHz
X _{13 MHz}
P _{E 16 MHz}
- ^{18 MHz}
FDV
not possible
472
436
354
315
Error in f_DIV
+ 0.03 %
+ 0.1 %
+ 0.03 %
+ 0.14 %
18.432 MHz
307
- 0.07 %
20 MHz
283
- 0.04 %
24 MHz
236
+ 0.03 %
25 MHz
226
- 0.22 %
30 MHz
189
+ 0.14 %
33 MHz
172
+ 0.24 %
36 MHz
157
+ 0.18 %
Data Sheet
273
2001-04-19