C165H Datasheet, PDF (267/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165H
Asynchronous/Synchr. Serial Interface
BG represents the content of the reload register S0BG (BR_VALUE), taken as unsigned
13-bit integer. FDV represents the content of the fractional divider register S0FDV
(FD_VALUE) taken as unsigned 9-bit integer. For example, typical asynchronous
baudrates are shown in Table 54.
Using the fractional divider and a module clock of 36 MHz (equal to the C165H CPU
clock) the available baudrate range is 2.25 MBaud down to 0.5364 Baud.
.
Table 54
Typical Asynchronous Baudrates using the Fractional Input Clock
Divider
Y ^fMOD
INAR_T ^{- 36MHz}
Desired
Baudrate
max. Baudrate
230.4 kBaud
115.2 kBaud
57.6
kBaud
38.4
kBaud
19.2
kBaud
min. Baudrate
BG
0
6
13
27
41
83
8191
FDV
0
367
367
367
367
367
1
Resulting
Baudrate
2.25
MBaud
230.399 kBaud
115.199 kBaud
57.5997 kBaud
38.3998 kBaud
19.1999 kBaud
0.53644 Baud
Deviation
0%
< 0.01 %
< 0.01 %
< 0.01 %
< 0.01 %
< 0.01 %
0%
IM P Note: The ApNote AP2423 provides a program ’ASC.EXE’ which allows to calculate
values for the S0FDV and S0BG registers depending on f_MOD, the requested
L ^{R baudrate, and the maximum deviation. Please contact your Infineon Technologies}
representative.
E ^E _{11.1.7.2 Baudrates in Synchronous Mode}
R ^{C For synchronous operation, the baudrate generator provides a clock with 4 times the rate}
P _{- EX} ^{of the established baudrate.(see Figure 87).}
Data Sheet
267
2001-04-19