C165H Datasheet, PDF (102/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165H
Interrupt and Trap Functions
PSW (FF10_H / 88_H)
15 14 13 12 11 10 9
ILVL
HLD
IEN _EN -
rw
rw rw -
SFR
87654
MUL
-
- USR0 _IP E
-
- rw rw rw
Reset Value: 0000_H
3210
Z VCN
rw rw rw rw
Bit
Function
N, C, V, Z, E, CPU status flags (Described in section “The Central Processing Unit”)
MULIP, USR0 Define the current status of the CPU (ALU, multiplication unit).
Y ^HLDEN
HOLD Enable (Enables External Bus Arbitration)
0: Bus arbitration disabled, P6.7...P6.5 may be used for general purpose I/O
1: Bus arbitration enabled, P6.7...P6.5 serve as BREQ, HLDA, HOLD, resp.
ILVL
INAR ^{- IEN}
CPU Priority Level
Defines the current priority level for the CPU
F_H: Highest priority level
0_H: Lowest priority level
Interrupt Enable Control Bit (globally enables/disables interrupt requests)
‘0’: Interrupt requests are disabled
‘1’: Interrupt requests are enabled
T CPU Priority ILVL defines the current level for the operation of the CPU. This bit field
IM ^{reflects the priority level of the routine that is currently executed. Upon entry into an}
P interrupt service routine this bit field is updated with the priority level of the request that
is being serviced. The PSW is saved on the system stack before. The CPU level
L ^{R determines the minimum interrupt priority level that will be serviced. Any request on the}
same or a lower level will not be acknowledged.
E ^{E The current CPU priority level may be adjusted via software to control which interrupt}
request sources will be acknowledged.
R ^{C PEC transfers do not really interrupt the CPU, but rather “steal” a single cycle, so PEC}
services do not influence the ILVL field in the PSW.
X _{Hardware traps switch the CPU level to maximum priority (ie. 15) so no interrupt or PEC}
Prequests will be acknowledged while an exception trap service routine is executed.
- ^{E Note: The TRAP instruction does not change the CPU level, so software invoked trap}
service routines may be interrupted by higher requests.
Interrupt Enable bit IEN globally enables or disables PEC operation and the
acceptance of interrupts by the CPU. When IEN is cleared, no interrupt requests are
accepted by the CPU. When IEN is set to '1', all interrupt sources, which have been
individually enabled by the interrupt enable bits in their associated control registers, are
globally enabled.
Note: Traps are non-maskable and are therefore not affected by the IEN bit.
Data Sheet
102
2001-04-19