C165H Datasheet, PDF (318/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165H
IOM-2 Interface Controller
MASK
ISTA
ST
ST
MRE
MDR
CIC
CIC
MER
MOS
MOS
MIE
MDA
4x
HDLC
4x
HDLC
MOCR
MAB
MOSR
Y _IOMINT
R Figure 109 MONITOR Interrupt Structure
A 14.4
C/I Channel Handler
The Command/Indication channel carries real-time status information between the
IN ^{- C165H and another device connected to the IOM.}
T 14.4.1 C/I0 - Command/Indication 0
IM ^{One C/I channel (called C/I0) conveys the commands and indications between the}
P _{C165H and an external layer-1 device. C/I0 channel access may be arbitrated via the}
TIC bus access protocol. In this case the arbitration is done in C/I channel 2 (timeslot 1),
L ^{R see Figure 102.}
E ^{E The C/I0 channel is accessed via register bit CIC0_D.CODR0 (in receive direction, layer-}
1 to layer-2) and register CIC0_D.CODX0 (in transmit direction, layer-2 to layer-1). The
C/I0 code is four bits long. In the receive direction, the code from layer-1 is continuously
R ^{C monitored, with an interrupt being generated anytime a change occurs (ISTA.CIC). A}
X ^{new code must be found in two consecutive IOM frames to be considered valid and to}
trigger a C/I code change interrupt status (double last look criterion).
P _{- E In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.}
14.4.2 C/I1 - Command/Indication 1
A second C/I channel (called C/I1) can be used to convey real time status information
between the C165H and various non-layer-1 peripheral devices. The C/I1 channel
consists of four or six bits in each direction.The width can be changed from 4bit to 6bit
by setting bit CIC_CMD.CICW.
The C/I1 channel is accessed via registers CIC1_D.CODR1 and CIC1_D.CODX1. A
change in the received C/I1 code is indicated by an interrupt status without double last
look criterion.
Data Sheet
318
2001-04-19