C165H Datasheet, PDF (193/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

C165H
External Bus Interface
RP0H (F108_H / 84_H)
SFR
Reset Value: - - XX_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKCFG
SALSEL CSSEL WRC
-
-
-
-
-
-
-
-
r
r
r
r
Bit
Function
WRC
CSSEL
RY _SALSEL
IMINA ^{T - CLKCFG}
Write Configuration
0: Pins WR and BHE operate as WRL and WRH signals
1: Pins WR and BHE operate as WR and BHE signals
Chip Select Line Selection (Number of active CS outputs)
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS lines at all
1 1: 5 CS lines: CS4...CS0 (Default without pulldowns)
Segment Address Line Selection (Number of active segment address outputs)
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 7-bit segment address: A22...A16
1 1: 2-bit segment address: A17...A16 (Default without pulldowns)
Clock Generation Mode Configuration
These pins define the clock generation mode, ie. the mechanism how the the
internal CPU clock is generated from the externally applied (XTAL1) input clock.
P _{Note: RP0H cannot be changed via software, but rather allows to check the current}
L ^R configuration.
E ^{E Precautions and Hints}
R ^{C • The external bus interface is enabled as long as at least one of the BUSCON registers}
has its BUSACT bit set.
X _{• PORT1 will output the intra-segment address as long as at least one of the BUSCON}
P^{registers selects a demultiplexed external bus, even for multiplexed bus cycles.}
E _{• Not all address areas defined via registers ADDRSELx may overlap each other. The}
- ^{operation of the EBC will be unpredictable in such a case. See chapter „Address Window}
Arbitration“.
• The address areas defined via registers ADDRSELx may overlap internal address
areas. Internal accesses will be executed in this case.
• For any access to an internal address area the EBC will remain inactive (see EBC Idle
State).
Data Sheet
193
2001-04-19