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C165H Datasheet, PDF (50/499 Pages) Infineon Technologies AG – EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT
C165H
Memory Organization
General Purpose Registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words within the
internal RAM. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to 16 word GPRs (R0,
R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte
GPRs are mapped onto the first eight word GPRs (see table below).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address
(independent of the current DPP register contents). Additionally, each bit in the currently
Y active register bank can be accessed individually.
Mapping of General Purpose Registers to RAM Addresses
R Internal RAM Address
<CP> + 1EH
A <CP> + 1CH
IN - <CP> + 1AH
<CP> + 18H
<CP> + 16H
T <CP> + 14H
IM P <CP> + 12H
<CP> + 10H
L R <CP> + 0EH
E E <CP> + 0CH
<CP> + 0AH
R C <CP> + 08H
<CP> + 06H
X <CP> + 04H
P E <CP> + 02H
- <CP> + 00H
Byte Registers
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RH7
RL7
RH6
RL6
RH5
RL5
RH4
RL4
RH3
RL3
RH2
RL2
RH1
RL1
RH0
RL0
Word Register
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
C165H supports fast register bank (context) switching. Multiple register banks can
physically exist within the internal RAM at the same time. Only the register bank selected
by the Context Pointer register (CP) is active at a given time, however. Selecting a new
active register bank is simply done by updating the CP register. A particular Switch
Context (SCXT) instruction performs register bank switching and an automatic saving of
the previous context. The number of implemented register banks (arbitrary sizes) is only
limited by the size of the available internal RAM.
Data Sheet
50
2001-04-19