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HYB18T256324F-16 Datasheet, PDF (54/80 Pages) Infineon Technologies AG – 256-Mbit GDDR3 DRAM [600MHz]
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.6 Read followed by Precharge on the same Bank









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Figure 37
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Read followed by Precharge on the same Bank
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1. tRAS requirement must also be met before issuing PRE command
2. RD and PRE commands are applied to the same bank.
3. Shown with nominal tAC and tDQSQ
4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
Data Sheet
54
Rev. 1.11, 04-2005
10292004-DOXT-FS0U