HYB18T256324F-16 Datasheet, PDF (14/80 Pages) Infineon Technologies AG – 256-Mbit GDDR3 DRAM [600MHz]

2.2
Functional Block Diagram
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
A0-A7,A9, A8/AP, A10-A11
BA0, BA1
Address buffer
A8/AP
Refresh
Counter
Row Addresses A0-A11, BA0-BA1
Row Address Buffer
Column Addresses A2-A7,A9
Column Address Buffer
CS#
RAS#
CAS#
WE#
RES
ZQ
CKE
CLK
CLK#
Row Decoder
Memory
Array
Bank 0
4096 x 512
x 32 bit
Row Decoder
Memory
Array
Bank 1
4096 x 512
x 32 bit
Row Decoder
Memory
Array
Bank 2
4096 x 512
x 32 bit
Row Decoder
Memory
Array
Bank 3
4096 x 512
x 32 bit
DLL
Output Buffers
Input Buffers
DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31
Figure 2 Functional Block Diagram
Data Sheet
14
Rev. 1.11, 04-2005
10292004-DOXT-FS0U