HYB18T256324F-16 Datasheet, PDF(43/80 Page) Infineon Technologies AG – 256-Mbit GDDR3 DRAM [600MHz]

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HYB18T256324F-16 Datasheet, PDF (43/80 Pages) Infineon Technologies AG – 256-Mbit GDDR3 DRAM [600MHz]

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HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

3.7.6

Write followed by DTERDIS

#, +

#,+

#O M

72

$4 $

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

!D DR

"#

7$ 1 3

$1

7,

72

$4 $

#,

$ $ $ $

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

"#

7$ 13

$1

72

7,

#,

.$

$4 $

$ $ $ $

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

$% 3

"#

7,

#,

7$ 1 3

$1

$ $ $ $

Figure 26 Write Command followed by DTERDIS

"#" ANK # O LU MNA DDRE S S

72 72 )4 %

$4 $ $ 4 %2 $ )3

$ $ A TA TO " # X

#O M # OM M AND

!D D R! D DRE SS"#

7,7 RITE , ATEN C Y

#, #! 3 ,A TE N CY

$% 3 $ ES E LE CT

.$ ./ 0O R$E S ELE CT

$O NgT# A RE

$A TA 4 ERM INA TION /FF

1. Write shown with nominal value of tDQSS.

2. WDQS can only transition when data is applied at the chip input and during pre- and postambles

3. A margin of one clock has been introduced in order to make sure that the data termination are still on when

the last Write data reaches the memory.

4. The minimum distance between Write and DTERDIS is (WL -CL + 4) clocks and always bigger than or equal

to 1. For (CL=6 / WL=2) and (CL=7 / WL=3) as well as for (CL=7 / WL=2) the minimum distance between Write

and DTERDIS is set to 1 clock. Please refer to table below:

Table 24 WL / CL

WL \ CL

5

6

7

2

1

1

1

3

2

1

1

4

3

2

1

Data Sheet

43

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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