HYB18T256324F-16 Datasheet, PDF(38/80 Page) Infineon Technologies AG – 256-Mbit GDDR3 DRAM [600MHz]

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HYB18T256324F-16 Datasheet, PDF (38/80 Pages) Infineon Technologies AG – 256-Mbit GDDR3 DRAM [600MHz]

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HYB18T256324Fâ[16/20/22]

256-Mbit DDR SGRAM

Functional Description

3.7.2 Write - Basic Sequence

#, +

#,+

#O M

72

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7,

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7,

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72

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./ 0

./ 0

./ 0

./ 0

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./0

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"#" A NK # OLUM NA D DRE SS

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./ 0. O/PE RA TION

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#O M # OM MAN D

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$ $A TA TO " #

7, 7 RITE, A TE NC Y

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Figure 21 Write Burst Basic Sequence

1. Shown with nominal value of tDQSS.

2. WDQS can only transition when data is applied at the chip input and during pre- and postambles.

3. When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High.

4. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown.

Data Sheet

38

Rev. 1.11, 04-2005

10292004-DOXT-FS0U

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