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TLE7809G Datasheet, PDF (42/52 Pages) Infineon Technologies AG – Integrated double low-side switch, high-side/LED driver, hall supply, wake-up inputs and LIN communication with embedded MCU (16kB Flash)
TLE7809G
General Product Characteristics
Table 14 Electrical Characteristics (cont’d)
VS = 13.5 V, Tj = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
Transfer Rate 20 kbit/s; 1 μs < τ = RL × Cbus < 5 μs
16.4.104 Duty cycle D1
D1
0.396 –
–
μs duty cycle 1:
THRec(max) = 0.744 × VS;
THDom(max) = 0.581 × VS;
VS = 7.0 … 18 V;
tbit = 50 μs;
D1 = tbus_rec(min) / 2 tbit;
(LIN Spec 2.0;
Line 3.3.1)
16.4.105 Duty cycle D2
D2
–
–
0.581 μs duty cycle 2:
THRec(min) = 0.422 × VS;
THDom(min) = 0.284 × VS;
VS = 7.6 … 18 V;
tbit = 50 μs;
D2 = tbus_rec(max) / 2 tbit;
(LIN Spec 2.0;
Line 3.3.2)
Transfer Rate 10.4 kbit/s; 1 μs < τ = RL × Cbus < 5 μs
16.4.106 Duty cycle D3
D3
0.417 –
–
μs duty cycle 3:
THRec(max) = 0.778 × VS;
THDom(max) = 0.616 × VS;
VS = 7.0 … 18 V;
tbit = 96 μs;
D3 = tbus_rec(min) / 2 tbit;
(LIN Spec 2.0;
Line 3.4.1)
16.4.107 Duty cycle D4
SPI Data Input Timing1)
D4
–
–
0.590 μs duty cycle 4:
THRec(min) = 0.389 × VS;
THDom(min) = 0.251 × VS;
VS = 7.6 … 18 V;
tbit = 96 μs;
D4 = tbus_rec(max) / 2 tbit;
(LIN Spec 2.0;
Line 3.4.2)
16.4.108
16.4.109
16.4.110
16.4.111
16.4.112
16.4.113
16.4.114
16.4.115
Clock period
Clock high time
Clock low time
Clock low before CSN low
CSN setup time
CLK setup time
Clock low after CSN high
DI setup time
tpCLK
tCLKH
tCLKL
tbef
tlead
tlag
tbeh
tDISU
250 –
–
ns –
125 –
–
ns –
125 –
–
ns –
125 –
–
ns –
250 –
–
ns –
250 –
–
ns –
125 –
–
ns –
50
–
–
ns –
Data Sheet
42
Rev. 3.01, 2008-04-15