TLE9871QXA20_15 Datasheet, PDF (36/122 Pages) Infineon Technologies AG – Microcontroller with PWM Interface and BLDC MOSFET Driver for Automotive Applications

9.3
Functional Description
TLE9871QXA20
DMA Controller
9.3.1 DMA Mode Overview
The DMA controller implements the following 13 hardware DMA requests:
• ADC1 complete sequence 1 done: DMA transfer is requested on completion of the ADC1 channel conversion
sequence.
• ADC1 exceptional sequence 2 (ESM) done: DMA transfer is requested on completion of the ADC1 conversion
sequence triggered by an exceptional measurement request.
• SSC1/2 transmit byte: DMA transfer is requested upon the completion of data transmission via SSC1/2
• SSC1/2: receive byte: DMA transfer is requested upon the completion of data reception via SSC1/2.
• ADC1 channel 0 conversion done: DMA transfer is requested on completion of the ADC1 channel 0
conversion.
• ADC1 channel 1 conversion done: DMA transfer is requested on completion of the ADC1 channel 1
conversion.
• ADC1 channel 2 conversion done: DMA transfer is requested on completion of the ADC1 channel 2
conversion.
• ADC1 channel 3 conversion done: DMA transfer is requested on completion of the ADC1 channel 3
conversion.
• ADC1 channel 4 conversion done: DMA transfer is requested on completion of the ADC1 channel 4
conversion.
• ADC1 channel 5 conversion done: DMA transfer is requested on completion of the ADC1 channel 5
conversion.
• ADC1 channel 6 conversion done: DMA transfer is requested on completion of the ADC1 channel 6
conversion.
• ADC1 channel 7 conversion done: DMA transfer is requested on completion of the ADC1 channel 7
conversion.
• Timer3 ccu6_int: DMA transfer is requested following a timer trigger.
Data Sheet
36
Rev. 1.0, 2015-04-30