TLE9871QXA20_15 Datasheet, PDF (19/122 Pages) Infineon Technologies AG – Microcontroller with PWM Interface and BLDC MOSFET Driver for Automotive Applications

TLE9871QXA20
Power Management Unit (PMU)
5.2.1 Block Diagram
The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules in
more detail.
e.g. for WDT 1
e.g. for cyclic
wake and sense
MON
PWM_IO
P0.0...P0.4
P1.0...P1.4
VS
Power Down Supply
I
LP_CLK
N
T
Peripherals
E
LP_CLK2
R
N
A
L
PMU-PCU
B
U
S
PMU-WMU
Power Supply Generation Unit
(PGU)
LDO for External Supply
VDDEXT
PMU-SFR
PMU-CMU
PMU-RMU
VDDP
VDDC
VDDEXT
PMU-Control
Power Management Unit
Power_Management_71.vsd
Figure 3 Power Management Unit Block Diagram
Table 4 Description of PMU Submodules
Mod.
Name
Modules
Power Down Independent supply voltage
Supply
generation for PMU
LP_CLK
(= 18 MHz)
- Clock source for all PMU
submodules
- Backup clock source for System
- Clock source for WDT1
LP_CLK2
(= 100 kHz)
Peripherals
Clock source for PMU
Peripheral blocks of PMU
Functions
This supply is dedicated to the PMU to ensure an
independent operation from generated power supplies
(VDDP, VDDC).
This ultra low power oscillator generates the clock for the
PMU.
This clock is also used as backup clock for the system in
case of PLL Clock failure and as an independent clock
source for WDT1.
This ultra low power oscillator generates the clock for the
PMU in Stop Mode and in the cyclic modes.
These blocks include the analog peripherals to ensure a
stable and fail-safe PMU startup and operation (bandgap,
bias).
Data Sheet
19
Rev. 1.0, 2015-04-30