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TC1797 Datasheet, PDF (33/190 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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TC1797
Introduction
⢠Overlay support with SRAM for calibration applications.
⢠Configurable wait state selection for different CPU frequencies.
⢠Endurance = 1000; minimum 1000 program/erase cycles per physical sector;
reduced endurance of 100 per 16 KB sector.
⢠Operating lifetime (incl. Retention): 20 years with endurance=1000.
⢠For further operating conditions see data sheet section âFlash Memory Parametersâ.
Data Flash Features and Functions
Note: Only available in PMU0.
⢠64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size.
⢠64 bit read interface.
⢠Erase/program one bank while data read access from the other bank.
⢠Programming one bank while erasing the other bank using an automatic
suspend/resume function.
⢠Dynamic correction of single-bit errors during read access.
⢠Sector architecture:
â Two sectors of equal size.
â Each sector separately erasable.
⢠128 byte pages to be written in one step.
⢠Operational control per command sequences (unlock sequences, same as those of
Program Flash) for protection against unintended operation.
⢠End-of-busy as well as error reporting with interrupt and bus error trap.
⢠Write state machine for automatic program and erase.
⢠Margin check for detection of problematic Flash bits.
⢠Endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per
sector are allowed, with a retention of min. 5 years.
⢠Dedicated DFlash status information.
⢠Other characteristics: Same as Program Flash.
Data Sheet
29
V1.1, 2009-04
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