TC1797 Datasheet, PDF (184/190 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
Electrical Parameters
5.3.11.4 E-Ray Interface Timing
The timings in this section are valid for the strong / sharp and strong / medium settings
of the output drivers, and for both A1 or A2 input pads. The timing parameters are not
subject to production test, but verified by design / characterization.
Table 32
Parameter
E-Ray Interface Timing (Operating Conditions apply), C_L = 25 pF
Symbol
Limit Values
Unit Notes
Min. Typ. Max.
Conditions
TxDA / TxDB Signal Timing at end of frame
Time span from last
t₆₀
BSS to FES without the
influence of quartz
tolerances d10Bit_Tx ¹⁾
CC 997.75 –
1002.25 ns
f_oscdd = 20MHz;
f_oscdd = 40MHz;
C_L = 25 pF
(TxDA, TXDB)
TxD data valid, from
f_sample flip-flop txd_reg
⇒ TxDA, TxDB,
(dTxAsym) ^{2) 3)}
|t₆₁ - t₆₂| CC –
– 1.5
ns Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
RxDA / RxDB Signal Timing at end of frame
Time span between last t₆₃
BSS and FES that is
properly decoded,
without influence of
quartz tolerances
d10Bit_Rx ^{1) 4) 5)}
SR 966 – 1046.1 ns f_oscdd = 20MHz;
f_oscdd = 40MHz;
C_L = 25 pF
(TxDA, TXDB)
RxD capture by f_sample,
RxDA / RxDB ⇒
sampling flip-flop,
(dRxAsym) ⁵⁾
|t₆₄ - t₆₅| CC –
– 3.0
ns Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
1) PLL jitter included.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quartz tolerance and PLL jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |t_F - t_R| ≤ 1 ns.
4)Limits of 966.5 ns and 1046 ns correspond to (30%, 70%) × V_DDP FlexRay standard
input thresholds.
Due to different input thresholds of the TC1797, a correcton of -0.5 ns and +0.1 ns has
been applied.
Data Sheet
180
V1.1, 2009-04