TC1797 Datasheet, PDF (162/190 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1797
5.3.6
E-Ray Phase Locked Loop (E-Ray PLL)
Electrical Parameters
Note: All PLL characteristics defined on this and the next page are not subject to
production test, but verified by design characterization.
Table 20 PLL Parameters of the System PLL(Operating Conditions apply)
Parameter
Symbol
Min.
Values
Unit Note /
Typ. Max.
Test Con
dition
Accumulated jitter at
D_{P_ERAY_I}
–
E_Ray module clock input¹⁾
– 0.5 ns –
Accumulated jitter at
SYSCLK pin²⁾
D_{P_ERAY_E}
–
– 0.8 ns –
VCO frequency range
f_{VCO_ERAY}
400
– 500 MHz –
VCO input frequency range f_{REF_ERAY}
20
– 40 MHz –
PLL base frequency³⁾
f_{PLLBASE_ERAY} 140
– 320 MHz –
PLL lock-in time
t_{L_ERAY}
–
– 200 µs –
1) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with f_OSC = 20MHz, K = 6, and
f_SAMPLE = 80 MHz.
2) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with f_OSC = 20MHz, K = 6, and
f_SAMPLE = 80 MHz.
3) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
the K factor after reset).
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
not exceed C_L = 20 pF with the maximum driver and sharp edge, except the E-Ray
output pins, which can be loaded with C_L = 25 pF. In case of applications with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
V_DDPF3 at pin G24 and V_SSOSC at pin F25, is limited to a peak-to-peak voltage of
V_PP = 100 mV for noise frequencies below 300 KHz and V_PP = 40 mV for noise
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
V_DDPF at pin G23 and V_SSOSC at pin F25, is limited to a peak-to-peak voltage of
V_PP = 100 mV for noise frequencies below 300 KHz and V_PP = 40 mV for noise
frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
158
V1.1, 2009-04