HYS64D64300GU Datasheet, PDF (27/40 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17 SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte# Description
0
Programmed SPD Bytes in E2PROM
1
Total number of Bytes in E2PROM
2
Memory Type (DDR = 07h)
3
Number of Row Addresses
4
Number of Column Addresses
5
Number of DIMM Ranks
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t_CK @ CL_max (Byte 18) [ns]
10
t_AC SDRAM @ CL_max (Byte 18) [ns]
11
Error Correction Support
12
Refresh Rate
13
Primary SDRAM Width
14
Error Checking SDRAM Width
15
t_CCD [cycles]
16
Burst Length Supported
17
Number of Banks on SDRAM Device
18
CAS Latency
19
CS Latency
20
Write Latency
21
DIMM Attributes
22
Component Attributes
23
t_CK @ CL_max -0.5 (Byte 18) [ns]
24
t_AC SDRAM @ CL_max -0.5 [ns]
25
t_CK @ CL_max -1 (Byte 18) [ns]
26
t_AC SDRAM @ CL_max -1 [ns]
512 MB
512 MB
×64
×72
1 Rank (×8) 1 Rank (×8)
PC3200U–30330
Rev 0.0
Rev 0.0
HEX
HEX
80
80
08
08
07
07
0D
0D
0B
0B
01
01
40
48
00
00
04
04
50
50
50
50
00
02
82
82
08
08
00
08
01
01
0E
0E
04
04
1C
1C
01
01
02
02
20
20
C1
C1
60
60
50
50
75
75
50
50
1 GByte
×64
2 Ranks (×8)
Rev 0.0
HEX
80
08
07
0D
0B
02
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
1 GByte
×72
2 Ranks (×8)
Rev 0.0
HEX
80
08
07
0D
0B
02
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
60
50
75
50
Data Sheet
27
Rev. 1.0, 2004-05