HYS64D64300GU Datasheet, PDF (16/40 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
CK R = 120 Ω ± 5%
DIMM
Connector
CK
3 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
1 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
Figure 6 Clock Net Wiring
DRAM1
DRAM2
DRAM3
DRAM4
DRAM5
DRAM6
DRAM1
Cap.
DRAM3
Cap.
DRAM5
Cap.
Cap.
Cap.
DRAM3
Cap.
Cap.
Cap.
4 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
2 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
DRAM1
DRAM2
Cap.
Cap.
DRAM5
DRAM6
DRAM1
Cap.
Cap.
Cap.
DRAM5
Cap.
Data Sheet
16
Rev. 1.0, 2004-05