HYS64D64300GU Datasheet, PDF (18/40 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 12 Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Values
Unit Note/Test Condition ¹⁾
Min.
Typ.
Max.
Input Leakage Current
I_I
–2
2
µA Any input 0 V ≤ V_IN ≤ V_DD;
All other pins not under test
= 0 V ⁸⁾⁹⁾
Output Leakage Current I_OZ
–5
Output High Current,
I_OH
—
Normal Strength Driver
Output Low
I_OL
16.2
Current, Normal Strength
Driver
5
–16.2
—
µA DQs are disabled;
0 V ≤ V_OUT ≤ V_DDQ ⁸⁾
mA V_OUT = 1.95 V ⁸⁾
mA V_OUT = 0.35 V ⁸⁾
1) 0 °C ≤ T_A ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, V_DDQ must be less than or equal to V_DD.
4) Peak to peak AC noise on V_REF may not exceed ± 2% V_{REF (DC)}. V_REF is also expected to track noise variations in V_DDQ.
5) V_TT is not applied directly to the device. V_TT is a system supply for signal termination resistors, is expected to be set equal
to V_REF, and must track variations in the DC level of V_REF.
6) V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until V_REF stabilizes.
9) Values are shown per DDR SDRAM component
Table 13 AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit
DDR400B
DDR333
Min. Max. Min. Max.
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
t_AC
t_DQSCK
t_CH
t_CL
t_HP
t_CK
–0.5 +0.5 –0.7 +0.7 ns
–0.6 +0.6 –0.6 +0.6 ns
0.45 0.55
0.45 0.55
t_CK
0.45 0.55
0.45 0.55
t_CK
min. (t_CL, t_CH) min. (t_CL, t_CH) ns
5
8
—
—
ns
6
12
7.5 12
ns
7.5 12
7.5 12
ns
DQ and DM input hold time
t_DH
0.4 —
0.45 —
ns
DQ and DM input setup time
t_DS
0.4 —
0.45 —
ns
Control and Addr. input pulse width t_IPW
2.2 —
2.2 —
ns
(each input)
Note/ Test
Condition ¹⁾
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
Data Sheet
18
Rev. 1.0, 2004-05
10042003-RYU3-RQON