TLE5011_11 Datasheet, PDF (22/45 Pages) Infineon Technologies AG – GMR Angle Sensor

TLE5011
Specification
3.8
Clock Supply (CLK Timing Definition)
The clock signal input “CLK” must fulfill certain requirements described in this section:
• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike filtered.
• The duty-cycle factor should be 0.5 but can deviate from the values limited by t_{CLKh(f_min)} and t_{CLKl(f_min)}.
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically.
t_CLKh
t_CLK
t_CLKl
Figure 9 CLK Timing Definition
V_H
V_L
t
Table 12 CLK Timing Specification
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
Input Frequency
CLK Duty Cycle ¹⁾
f_CLK
3.8
CLK_DUTY
30
4.00
4.2
50
70
MHz
%
CLK rise time
t_CLKr
-
-
20
ns
CLK fall time
t_CLKf
-
-
20
ns
PLL Frequency
f_PLL
-
100
-
MHz
Digital Clock
f_DIG
-
25
-
MHz
Digital Clock Periode
t_DIG
-
40
-
ns
1) Minimum duty-cycle factor: t_{CLKh(f_min)} / t_{CLK(f_min)} with t_{CLK(f_min)} = 1 / f_{CLK(f_min)}
Maximum duty-cycle factor: t_{CLKh(f_max)} / t_{CLK(f_min)}with t_{CLKh(f_max)} = t_{CLK(f_min)} - t_CLKl(min)
Notes
from V_L to V_H
from V_H to V_L
f_CLK * 25
( 25 / 4 ) * f_CLK
4 / (25 * f_CLK)
3.9
Synchronous Serial Communication Interface (SSC)
The 3-pin SSC interface has a bidirectional data line (open drain), a serial clock signal, and Chip Select.
The SSC interface is designed to communicate with a microcontroller with bi-directional SSC interface supporting
open drain. Other microcontrollers may require an external NPN transistor.
This allows communication with SPI-compatible devices.
Final Data Sheet
22
V2.0, 2011-03