HYS72T32000GR Datasheet, PDF (19/24 Pages) Infineon Technologies AG – DDR2 Registered DIMM Modules

HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Byte# Description
Note:
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
Speed
Grade
SPD Entry
Value
Hex Value
32 Address and Command Setup Time (tIS)
-5
0.60 ns
60
-3.7
0.50 ns
50
-3
0.45 ns
45
33 Address and Command Hold Time (tIH)
-5
0.60ns
60
-3.7
0.50 ns
50
-3
0.45ns
45
34 Data Input Setup Time (tDS)
-5
0.40 ns
40
-3.7
0.35 ns
35
-3
0.30 ns
30
35 Data Input Hold Time (tDH)
-5
0.40 ns
40
-3.7
0.35 ns
35
-3
0.30 ns
30
36 Write Recovery Time (tWR)
all
15 ns
3C
37 Internal Write to Read Command delay (tWTR)
-5
10 ns
28
-3.7 & -3
7.5 ns
1E
38 Internal Read to Precharge delay (tRTP)
all
7.5 ns
1E
39 Not used
not used
00
40 Extension of Byte 41 tRC and Byte 42 tRFC
all
00
41 Minimum Core Cycle Time (tRC)
-5 & -3.7
60 ns
3C
-3
57 ns
39
42 Min. Auto Refresh Command Cycle Time (tRFC)
all
75 ns
4B
43 Maximum Clock Cycle Time tck
all
8 ns
80
44 Max. DQS-DQ Skew (tDQSQmax.)
-5
0.35 ns
23
-3.7
0.30 ns
1E
-3
0.25 ns
19
45 Read Data Hold Skew Factor (tQHS)
-5
0.45 ns
2D
-3.7
0.40 ns
28
-3
0.35 ns
23
46 PLL Relock Time
15.0 µs
0F
47-61 Reserved for “Delta Temperature in SPD”
see note 1
00
62 SPD Revision
Revision 1.0
10
63 Checksum for Bytes 0 - 62
-5
7D
7E
B6
-3.7
tbd.
tbd.
tbd.
-3
tbd.
tbd.
tbd.
64 Manufacturers JEDEC ID Code
INFINEON
C1
65-71 Not used
not used
00
72 Module Assembly Location
XX
73-90 Module Part Number
XX
91-92 Module Revision Code
XX
93-94 Module Manufacturing Date
Year/Week Code
XX
95-98 Module Serial Number
Serial Number
XX
99-127 Manufacturer’s Specific Data
blank
FF
128-255 Open for Customer use
blank
Note 1 : Will be used for future SPD Code Revisions. For details of “Delta Temperature in SPD” see JEDEC ballot JC-
42.5 Item # 1468.
INFINEON Technologies
19
2.04