HYS72T32000GR Datasheet, PDF (15/24 Pages) Infineon Technologies AG – DDR2 Registered DIMM Modules

HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.5 I_DD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
Parameter
Symbol
-5
PC2-3200
-3.7
PC2-4200
-3
PC2-5300
Unit
3-3-3
4-4-4
4-4-4
CAS Latency
CL(IDD)
3
4
4
tCK
Clock Cycle Time
tCK(IDD)
5
3.75
3
ns
Active to Read or Write delay
tRCD(IDD)
15
15
12
ns
Active to Active / Auto-Refresh command period tRC(IDD)
60
60
57
ns
Active bank A to Active bank B command delay tRRD(IDD)
7.5
7.5
7.5
ns
Active to Precharge Command
tRASmin(IDD)
tRASmax(IDD)
45
70000
45
70000
45
ns
70000
ns
Precharge Command Period
tRP(IDD)
15
15
12
ns
Auto-Refresh to Active / Auto-Refresh command
period
tRFC(IDD)
75
75
75
ns
Average periodic Refresh interval
tREFI
7.8
7.8
7.8
µs
4.5 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The cur-
rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State _min.
typ.
Enabled ODT current per DQ
A6 = 0, A2 = 1
5
6
added IDDQ current for ODT enabled;
IODTO
ODT is HIGH; Data Bus inputs are FLOATING
A6 = 1, A2 = 0 2.5
3
Active ODT current per DQ
A6 = 0, A2 = 1 10
12
added IDDQ current for ODT enabled;
IODTT
ODT is HIGH; worst case of Data Bus inputs
A6 = 1, A2 = 0
5
6
are STABLE or SWITCHING.
note: For power consumption calculations the ODT duty cycle has to be taken into account
max.
7.5
3.75
15
Unit
mA/DQ
mA/DQ
mA/DQ
7.5 mA/DQ
INFINEON Technologies
15
2.04