HYS72T32000GR Datasheet, PDF (11/24 Pages) Infineon Technologies AG – DDR2 Registered DIMM Modules

HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
3.0 Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
Voltage on any pins relative to V_SS
V_IN, V_OUT
– 0.5
2.3
V
Voltage on V_DD relative to V_SS
V_DD
– 1.0
2.3
V
Voltage on V_{DD Q} relative to V_SS
Storage temperature range
V_DDQ
T_STG
– 0.5
-55
2.3
+100 ^oC
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
3.1 Operating Temperature Range
Parameter
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Symbol
TOPR
TCASE
Limit Values
min.
max.
0
+55
0
+95
Unit Notes
o_C
o_{C 1 - 4}
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3. Above 85^oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85^oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit Notes
min.
nom.
max.
Device Supply Voltage
V_DD
1.7
1.8
1.9
V-
Output Supply Voltage
V_DDQ
1.7
1.8
1.9
V 1)
Input Reference Voltage
V_REF
0.49 x V_DDQ
0.5 x V_DDQ
0.51 x V_DDQ
V 2)
EEPROM Supply Voltage
V_DDSPD
1.7
–
3.6
V
DC Input Logic High
V_{IH (DC)}
V_REF + 0.125
–
V_DDQ + 0.3
V
DC Input Logic Low
V_{IL (DC)}
– 0.30
–
V_REF – 0.125
V
In / Output Leakage Current I_L
–5
–
5
µA 3)
1 Under all conditions, V_DDQ must be less than or equal to V_DD
2 Peak to peak AC noise on V_REF may not exceed ± 2% V_{REF (DC)}.V_REF is also expected to track noise variations in V_DDQ.
3 For any pin on the DIMM connector under test input of 0 V ≤ V_IN ≤ V_DDQ + 0.3 V.
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