HYS72T32000GR Datasheet, PDF (18/24 Pages) Infineon Technologies AG – DDR2 Registered DIMM Modules

HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
6.0 Serial Presence Detect Codes for Registered DIMM Modules
Byte# Description
Note:
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
Speed
Grade
SPD Entry
Value
Hex Value
0 Number of SPD Bytes
all
128
80
1 Total Bytes in Serial PD
all
256
08
2 Memory Type
all
DDR2-SDRAM
08
3 Number of Row Addresses
all
13
0D
4 Number of Column Addresses
all
10 / 11
0A
0A
0B
5 Number of DIMM Ranks, Package and Height
all
1/2
60
61
60
6 Module Data Width
all
x72
48
7 Not used
all
not used
00
8 Module Interface Levels
all
SSTL_1.8
05
9 Min. Clock Cycle Time at CAS Latency = 5
-5
5 ns
50
-3.7
3.7 ns
3D
-3
3 ns
30
10 SDRAM Access Time from Clock at CL = 5
-5
0.6 ns
60
-3.7
0.5 ns
50
-3
0.45 ns
45
11 DIMM Configuration Type
all
ECC
02
12 Refresh Rate/Type
all
7.8 µs / SR
82
13 SDRAM Width, Primary
all
x8, x4
08
08
04
14 Error Checking SDRAM Data Width
all
x8, x4
08
08
04
15 Not used
all
not used
00
16 Burst Length Supported
all
4&8
0C
17 Number of SDRAM Banks
all
4
04
18 Supported CAS Latencies
all
5, 4, 3
38
19 Not used
all
not used
00
20 DIMM Type Information
all
Reg. DIMM
01
21 SDRAM Module Attributes
all
see note 1
00
22 SDRAM Device Attributes: General
all incl. weak driver
01
23 Min. Clock Cycle Time at CAS Latency = 4
-5
5 ns
50
-3.7
3.7 ns
3D
-3
3 ns
30
24 SDRAM Access Time from Clock at CL = 4
-5
0.6 ns
60
-3.7
0.5 ns
50
-3
0.45 ns
45
25 Min. Clock Cycle Time at CAS Latency = 3
all
5 ns
50
26 SDRAM Access Time from Clock at CL = 3
all
0.6 ns
60
27 Minimum Row Precharge Time (tRP)
-5 & -3.7
15 ns
3C
-3
12 ns
30
28 Minimum Row Act. to Row Act. Delay (tRRD)
all
7.5 ns
1E
29 Minimum RAS to CAS Delay (tRCD)
-5 & -3.7
15 ns
3C
-3
12 ns
30
30 Minimum RAS Pulse Width (tRAS)
all
45 ns
2D
31 Module Density (per rank)
all
40
40
80
INFINEON Technologies
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