TDA7210V_10 Datasheet, PDF (16/44 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7210V
Functional Description
2.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of
up to 100 kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local
oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels)
for sbsequent circuits. The self-adjusting threshold on pin 19 its generated by RC-term or peak detector depending
on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in
Chapter 3.5.
2.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An
external RC network is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output
is connected to the PDO pin (Pin 26). This output can be used as an indicator for the received signal strength to
use in wake-up circuits and as a reference for the data slicer in ASK mode. Note that the RSSI level is also output
in case of FSK mode.
2.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode
is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following
table. The supply current drawn in this case is typically 50 nA.
Table 6 PDWN Pin Operating States
PDWN
Open or tied to ground
Tied to V_CC
Operating State
Powerdown Mode
Receiver On
Data Sheet
16
Revision 1.1, 2010-06-18