TDA7210V_10 Datasheet, PDF (15/44 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7210V
Functional Description
Table 4 CSEL Pin Operating States
CSEL
Open
Shorted to ground
Crystal Frequency
6.xx MHz
13.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown in Chapter 3.3, the quartz
frequency calculation is explained in Chapter 3.4.
2.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a
bandpass-characteristic centred around 10.7 MHz. It has a typical input impedance of 330 Ω to allow for easy
interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator
(RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen
in Figure 6. This signal is used to demodulate ASK-modulated receive signals in the subsequent baseband
circuitry. The RSSI output is applied to the modulation format switch, to the Peak Detector input and to the AGC
circuitry.
In order to demodulate ASK signals the MSEL pin has to be left open as described in the next chapter.
2.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter
output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO.
The demodulator gain is typically 200 μV/kHz. The passive loop filter output that is comprised fully on chip is fed
to both the VCO and the modulation format switch described in more detail below. This signal is representing the
demodulated signal with high frequencies applied to the demodulator demodulated to logic ones and low
frequencies demodulated to logic zeroes. Please note that due to this behaviour a sign inversion of the data occurs
in case of high-side injection of the local oscillator at receive frequencies below 840 or 420 MHz, respectively.
The modulation format switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL
pin (Pin 14) as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits.
The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset produced by the demodulator
in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle
of operation of the switch are described in Chapter 3.6.
Table 5 MSEL Pin Operating States
MSEL
Open
Shorted to ground
Modulation Format
ASK
FSK
The demodulator circuit is switched off in case of reception of ASK signals.
2.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100 kHz used as a voltage follower and two 100 kΩ on-
chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection
of the capacitor values is described in Chapter 3.6.
Data Sheet
15
Revision 1.1, 2010-06-18