TDA7210V_10 Datasheet, PDF (14/44 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7210V
Functional Description
2.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 20 to 27 dB (depending on the matching). The gain
figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO
(Pin 4) and the Mixer Inputs MI and MIX (Pins 6 and 7). The noise figure of the LNA is approximately 3 dB, the
current consumption is 500 μA. The gain can be reduced by approximately 18 dB. The switching point of this AGC
action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is
compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI
level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be
generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3 V output generated from the internal bandgap voltage and the THRES pin as described in Chapter 3.1. The time
constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 2) and should be
chosen along with the appropriate threshold voltage according to the intended operating case and interference
scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is
described in Chapter 3.1.
2.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400-440 MHz/810-870 MHz to
the intermediate frequency (IF) at 10.7 MHz with a voltage gain of approximately 24 dB (depending on the
matching) by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced
only single-ended, the unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low
pass filter with a corner frequency of 20 MHz in order to suppress RF signals to appear at the IF output (IFO pin).
The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 Ω
to facilitate interfacing the pin directly to a standard 10.7 MHz ceramic filter without additional matching circuitry.
2.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with
charge pump and a loop filter and is fully implemented on-chip. The VCO is including on-chip spiral inductors and
varactor diodes. It’s nominal centre frequency is 840 MHz, the operating range guaranteed over the temperature
range specified is 820 to 860 MHz. Depending on whether high- or low-side injection of the local oscillator is used
the receive frequency ranges are 810 to 840 MHz and 840 to 870 MHz or 400 to 420 MHz and 420 to 440 MHz
(see also Chapter 3.4). No additional external components are necessary.
The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. In case of
operation in the 400 to 440 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled
by the selection pin FSEL (Pin 9) as described in the following table. The overall division ratio of the divider chain
can be selected to be either 128 or 64, depending on the frequency of the reference oscillator quartz (see below
and Chapter 3.4). The loop filter is also realised fully on-chip.
Table 3 FSEL Pin Operating States
FSEL
Open
Shorted to ground
RF Frequency
400-440 MHz
810-870 MHz
2.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 6 and 13 MHz range as the
overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 15) pin according to the
following table.
Data Sheet
14
Revision 1.1, 2010-06-18