TLE9869QXA20_15 Datasheet, PDF (103/122 Pages) Infineon Technologies AG – Microcontroller with LIN and H-Bridge MOSFET Driver for Automotive Applications

29.7
High-Speed Synchronous Serial Interface
TLE9869QXA20
Electrical Characteristics
29.7.1 SSC Timing Parameters
The table below provides the SSC timing in the TLE9869QXA20.
Table 33 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
V_S = 5.5 V to 28 V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Min.
Typ. Max.
SCLK clock period
t₀
1) _{2 * TSSC –}
–
MTSR delay from SCLK
t₁
10
–
–
ns
MRST setup to SCLK
t₂
10
–
–
ns
MRST hold from SCLK
t₃
15
–
–
ns
1) T_SSCmin = T_CPU = 1/f_CPU. If f_CPU = 20 MHz, t₀ = 100 ns. T_CPU is the CPU clock period.
2) Not subject to production test, specified by design.
Note /
Number
Test Condition
2) _{VDDP > 2.7 V}
2) _{VDDP > 2.7 V}
2) _{VDDP > 2.7 V}
2) _{VDDP > 2.7 V}
P_7.1.1
P_7.1.2
P_7.1.3
P_7.1.4
t₀
SCLK¹⁾
t₁
t₁
MTSR¹⁾
t₂
t₃
MRST¹⁾
Data
valid
t₁
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
Figure 36 SSC Master Mode Timing
SSC_Tmg1
Data Sheet
103
Rev. 1.0, 2015-04-30