ICS872S480 Datasheet, PDF (9/20 Pages) Integrated Device Technology – Differential-to-HSTL Zero Delay Clock Generator

ICS872S480 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Applications Information
Clock Redundancy and Reference Selection
The ICS872S480 accepts two differential input clocks, CLK0, nCLK0
and CLK1, nCLK1, for the purpose of redundancy. Only one of these
clocks can be selected at any given time for use as the reference.
CLK0, nCLK0 is defined as the initial, or primary clock, while the
remaining clock is the redundant or secondary clock. The output
signal CLK_IND indicates which clock input is being used as the
reference (LOW = CLK0, nCLK0, HIGH = CLK1, nCLK1).
Failure Detection and Alarm Signaling
Within the ICS872S480 device, CLK0, nCLK0 and CLK1, nCLK1 are
continuously monitored for failures. A failure on either of these clocks
is detected when one of the clock signals is stuck HIGH or LOW for
at least 1 period of the feedback. Upon detection of a failure, the
corresponding loss-of-reference signal, LOR0 or LOR1, will be set
HIGH. The input clocks are continuously monitored and the
loss-of-reference signals will continue to reflect the real-time status of
each input clock.
Manual Clock Switching
When input signal AUTO_SEL is driven LOW, the clock specified by
REF_SEL will always be used as the reference, even when a clock
failure is detected at the reference. In order to switch between CLK0,
nCLK0 and CLK1, nCLK1 as the reference clock, the level on
REF_SEL must be driven to the appropriate level. When the level on
REF_SEL is changed, the selection of the new clock will
take place, and CLK_IND will be updated to indicate which clock is
now supplying the reference to the PLL.
Dynamic Clock Switching
The Dynamic Clock Switching (DCS) process serves as an automatic
safety mechanism to protect the stability of the PLL when a failure
occurs on the reference.
When input signal AUTO_SEL is not driven HIGH, an internal pullup
pulls it HIGH so that DCS is enabled. If DCS is enabled and a failure
occurs on the initial clock, the ICS872S480 device will check the
status of the secondary clock. If the secondary clock is detected as a
good input clock, the ICS872S480 will automatically de-select the
initial clock as the reference and multiplex in the secondary clock.
When a successful switch from the initial to secondary clock has
been accomplished, CLK_IND will be updated to indicate the new
reference. If and when the fault on the initial clock is corrected, the
corresponding loss-of-reference flag will be updated to represent this
clock as good again. Once updated, the DCS will undergo an
automatic clock switch. See the Dynamic Clock Switch State
Diagram and for additional details on the functionality of the Dynamic
Clock Switching circuit.
Output Transitioning
After a successful DCS initiated clock switch, the internal PLL of the
ICS872S480 will begin slewing to phase/frequency alignment of the
newly selected clock input. The PLL will achieve lock to the new input
with minimal phase disturbance at the outputs.
Recommended Power-up Sequence
1.Before startup, set AUTO_SEL low so the PLL will operate in
manual switch mode, plus set REF_SEL low to ensure that the
primary reference clock, CLK0, nCLK0, is selected. This will
ensure that during startup, the PLL will acquire lock using the
primary reference clock input.
2.Once powered-up, and assuming a stable clock is present at the
primary clock input, the PLL will begin to phase/frequency slew as
it attempts to achieve lock with the input reference clock.
3.Drive AUTO_SEL HIGH to enable DCS mode.
Alternate Power-up Sequence
If both input clocks are valid before power up, the part may be
powered-up in DCS mode. However, it cannot be guaranteed that the
PLL will achieve lock with one specific input clock.
1.Before startup, leave AUTO_SEL floating and the internal pullup
will enable DCS mode.
2.Once powered up, the PLL will begin to phase/frequency slew as it
attempts to achieve lock with one of the input reference clocks.
ICS872S480BK REVISION A APRIL 19, 2011
9
©2011 Integrated Device Technology, Inc.