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| ICS872S480 Datasheet, PDF (5/20 Pages) Integrated Device Technology – Differential-to-HSTL Zero Delay Clock Generator | |||
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ICS872S480 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
IIH
IIL
VPP
VCMR
Input
High Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Input
Low Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-10
-150
0.15
0.3
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Typical
Maximum
150
10
1.75
VDD â 0.85
Units
µA
µA
µA
µA
V
V
Table 4D. HSTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
VOX
Output Crosspoint Voltage,
NOTE 1
VOUT_SEL = 0
VOUT_SEL = 1
VOD
Differential Output Voltage;
NOTE 1
VOUT_SEL = 0
VOUT_SEL = 1
NOTE 1: Outputs terminated with 50⦠to ground.
Minimum
0.7
0.6
0.8
0.8
Typical
0.8
0.7
0.9
0.9
Maximum
0.9
0.8
1.0
1.0
Units
V
V
V
V
Table 5. Input Frequency Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
FIN
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
FSEL = 1
FSEL = 0
485
350
Typical
Maximum
950
562.5
Units
MHz
MHz
ICS872S480BK REVISION A APRIL 19, 2011
5
©2011 Integrated Device Technology, Inc.
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