ICS872S480 Datasheet, PDF (6/20 Pages) Integrated Device Technology – Differential-to-HSTL Zero Delay Clock Generator

ICS872S480 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 6. AC Characteristics, V_DD = 3.3V ± 5%, T_A = 0°C to 70°C
Symbol Parameter
Test Conditions
f_OUT
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 2
tdyn(Ø) Dynamic Phase Offset; NOTE 7
pdev
Output Period Deviation; NOTE 3, 7
f_OUT = 400MHz
f_OUT = 533.3MHz
f_OUT = 666.6MHz
f_OUT = 800MHz
f_OUT = 400MHz
f_OUT = 533.3MHz
f_OUT = 666.6MHz
f_OUT = 800MHz
tsk(o) Output Skew; NOTE 2, 4
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3, 7
t_L
t_Ldcs
PLL Lock Time; NOTE 7
DCS PLL Lock Time; NOTE 6, 7
t_SLEW
VOUT_SEL = 0
Output Slew Rate;
NOTE 5
VOUT_SEL = 1
odc
Output Duty Cycle
f_OUT = 400MHz
f_OUT = 533.3MHz
f_OUT = 666.6MHz
f_OUT = 800MHz
f_OUT = 400MHz
f_OUT = 533.3MHz
f_OUT = 666.6MHz
f_OUT = 800MHz
Minimum
350
-25
-50
-50
-50
2.00
2.00
2.00
2.50
2.00
2.00
2.50
3.00
47
Typical
1.7
3.50
4.25
4.25
5.25
3.85
4.50
4.65
5.65
Maximum
950
75
50
50
50
±20
±25
±20
±20
100
20
25
3
5.75
6.50
6.75
8.65
6.35
6.85
7.25
8.25
53
Units
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
µs
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable. Characterized using HSTL input level of 900mV, swing centered around 0.6V.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: This parameter is defined as the maximum output period deviation during a dynamic switch event with reference inputs 180° out of
phase. This does not factor in any cycle-to-cycle jitter seen on the input or output.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 5: Output slew rate is measured at V_OX ± 150mV for VOUT_SEL = 0 and V_OX ±135mV for VOUT_SEL = 1.
NOTE 6: This parameter is defined as PLL lock time after a dynamic switch event with reference inputs 180° out of phase.
NOTE 7: This parameter is guaranteed by characterization. Not tested in production.
ICS872S480BK REVISION A APRIL 19, 2011
6
©2011 Integrated Device Technology, Inc.