ICS872S480 Datasheet, PDF (2/20 Pages) Integrated Device Technology – Differential-to-HSTL Zero Delay Clock Generator

ICS872S480 Data Sheet
Block Diagram
VOUT_SEL
OE
Pulldown
Pullup
PLL_Bypass
Pulldown
CLK0 ^Pullup
nCLK0 ^Pulldown
LOR0
CLK1 ^Pullup
nCLK1 ^Pulldown
Activity
Detector
0
1
Activity
Detector
LOR1
CLK_IND
REF_SEL
Pulldown
Dynamic
Switch
Logic
1
0
AUTO_SEL
Pullup
FB_IN ^Pullup
nFB_IN ^Pulldown
Pullup
FREQ_SEL
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
PD
+
CP
VCO
+
LF
1
Output
Divider
0
Q0, nQ0
Q1, nQ1
QFB, nQFB
ICS872S480BK REVISION A APRIL 19, 2011
2
©2011 Integrated Device Technology, Inc.