ICS872S480 Datasheet, PDF (7/20 Pages) Integrated Device Technology – Differential-to-HSTL Zero Delay Clock Generator

ICS872S480 Data Sheet
Parameter Measurement Information
3.3V ± 5%
3.3V ± 5%
V_DD
V_DDA
HSTL
GND
0V
3.3V Output Load AC Test Circuit
SCOPE
Qx
nQx
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
V_DD
nCLK0, nCLK1
V
PP
CLK0, CLK1
GND
Cross Points
V
CMR
Differential Input Level
nQ[0:1]
Q[0:1]
tcycle n
➤
tcycle n+1
➤
| | ^{tjit(cc) =} tcycle n – tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
nQx
Qx
nQy
Qy
t sk(o)
Output Skew
nCLK[0:1]
CLK[0:1]
nFB_IN
FB_IN
➤ t(Ø)
t(Ø)mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø)_mean is the
average of the sampled cycles measured on controlled edges)
nQ[0:1]
Q[0:1]
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Static Phase Offset
Output Duty Cycle/Pulse Width/Period
ICS872S480BK REVISION A APRIL 19, 2011
7
©2011 Integrated Device Technology, Inc.